Impact of Different Interfaces on Failure Mode

In semiconductor world, there is a new paradigm shift from chip-scaling to system-scaling to meet the ever-increasing electronic system demands in power saving, performance, and functionality (including memory bandwidth) increase, form factor improvement and cost reduction. This shift is also triggered by the growing concerns for industry to sustain Moore's Law. Innovations on wafer-based interconnect enable advanced packaging, that, in turn, enables system scaling and paradigm shift from transistor scaling. The innocations present in this speech include wafer-level-packaging (fan-in and fan-out), through-Si-via (3DIC and interposer) and ultra-thin Package-on-Package for both high performance and smart mobile applications. We also show that the industry can not only leverage wafer interconnect technologies, but also re-invent micro-electronics so that we can continue delivering more advanced systems, whether or not Moore's Law can be sustained.